1. Field of the Invention
The present invention relates to electrical circuits, and more particularly to testing of electrical circuits.
2. Description of Related Art
The increased complexity of electrical circuits has created new challenges for circuit testing. For example, in the integrated circuit area, the increased integration density and high speed create unpredictabilities that complicate testing of embedded signals as illustrated by the following example.
FIG. 1 shows an integrated circuit 110 which includes processor 114 and peripheral device 118. Device 118 is, for example, a serial port that receives data on pin 122. Port 118 asserts an interrupt signal INT for processor 114 when data is received. Signal INT is embedded, i.e., it is inaccessible from any integrated circuit pin.
Processor 114 is clocked by a clock signal CLK1. When clock CLK1 is high, processor 114 samples the signal INT and latches the signal in latch 126. When clock CLK1 is low, processor 114 latches the signal in latch 130 and uses the latched signal INTP.
Peripheral 118 is clocked by a different clock (not shown) asynchronous with respect to clock CLK1.
During testing, the integrated circuit is operated so that the signal INT is asserted at predetermined periods of time. The output signals of the integrated circuit are then compared to predetermined values obtained by simulation.
Because the clocks clocking the peripheral 118 and the processor 114 are asynchronous with respect to each other, and because of operating temperature and process variations, the exact moment of time when signal INT will be asserted during testing is difficult or impossible to predict. At high clock frequencies, signal INT can be asserted during any pulse within a range of pulses of clock CLK1. If the clock CLK1 pulse during which INT is asserted is different from the pulse predicted by simulation, the tester results will differ from the simulation results, indicating a false failure.
A typical solution is to move the edges of the input signals of circuit 110 that control the embedded signal INT until an operating point is found such that the output of the integrated circuit matches the output predicted from simulation. This process, however, is often difficult and time consuming, especially if the signal INT is embedded far into the integrated circuit. Further, due to process variations, the operating point varies from one integrated circuit to another. Moreover, even for the same circuit, the operating point varies with temperature and frequency. Finding the operating point for each integrated circuit and for each temperature and frequency is a difficult and time consuming task. In addition, if the integrated circuit is faulty, time is wasted searching for an operating point which does not exist.
Thus, there is a need for a testing technique which would allow testing complex electrical circuits including high density integrated circuits having asynchronous embedded signals, and which would allow the use of existing automatic testers and existing simulation programs but which would make the testing simpler and faster by eliminating the need to find a separate operating point for every integrated circuit and every temperature and frequency.